A Two Stage Template Matching Algorithm and Its Implementation on FPGA

AKTAŞ H., Sever R., TÖREYİN B. U.

23nd Signal Processing and Communications Applications Conference (SIU), Malatya, Türkiye, 16 - 19 Mayıs 2015, ss.2214-2217 identifier identifier

  • Yayın Türü: Bildiri / Tam Metin Bildiri
  • Doi Numarası: 10.1109/siu.2015.7130315
  • Basıldığı Şehir: Malatya
  • Basıldığı Ülke: Türkiye
  • Sayfa Sayıları: ss.2214-2217
  • Anahtar Kelimeler: Template Matching, Sum of Absolute Differences, Field-Programmable-Gate-Array (FPGA), Parallel Processing, Memorry Adressing, Unmanned Air Vehicle (UAV)
  • Akdeniz Üniversitesi Adresli: Evet

Özet

In this paper, to decrease the computational cost and number of cycles in Template Matching Algorithm, a novel two-stage algorithm is proposed. The Sum of Absolute Differences method is used for matching. The proposed algorithm is implemented on Field-Programmable-Gate-Array (FPGA). The algorithm is accelerated with the effective usage of Block RAMs distributed on FPGA. Thus, the proposed algorithm became fast enough for real time object tracking applications on UAVs.