SEVER, R. 2004. A high speed FPGA implementation of the Rijndael algorithm. Euromicro Symposium on Digital System Design, 2004. , (Rennes, France), 358-362.

SEVER, R., (2004). A high speed FPGA implementation of the Rijndael algorithm . Euromicro Symposium on Digital System Design, 2004. (pp.358-362). Rennes, France

SEVER, REFİK. "A high speed FPGA implementation of the Rijndael algorithm," Euromicro Symposium on Digital System Design, 2004., Rennes, France, 2004

SEVER, REFİK. "A high speed FPGA implementation of the Rijndael algorithm." Euromicro Symposium on Digital System Design, 2004. , Rennes, France, pp.358-362, 2004

SEVER, R. (2004) . "A high speed FPGA implementation of the Rijndael algorithm." Euromicro Symposium on Digital System Design, 2004. , Rennes, France, pp.358-362.

@conferencepaper{conferencepaper, author={REFİK SEVER}, title={A high speed FPGA implementation of the Rijndael algorithm}, congress name={Euromicro Symposium on Digital System Design, 2004.}, city={Rennes}, country={France}, year={2004}, pages={358-362} }